This invention relates to the field of semiconductor circuit technologies. More particularly, embodiments of this invention are directed to clock frequency multiplier circuits.
Electronic systems on printed circuit boards (PCB) often have limitations on the maximum allowable clock frequencies due to EMI concerns and signal coupling and trace lengths of the PCB connections. However, integrated circuits used on the electronic systems require increasingly faster clocks for signal processing and computation. In order to create a faster clock from a system clock, clock doublers are often used. In some of these systems, such as systems using a SoundWire interface, the clock frequency may be the same as the data rate. In that case, a clock doubler is required for data recovery.
Conventional clock frequency doubling circuits often use phase locked loop (PLL) or frequency locked loop (FLL) circuits. An alternative conventional design to create a clock with a double frequency of the input is to generate pulses on both the positive and negative going edges of the input clock. However, these conventional techniques have limitations that make them unsuitable for certain applications, as described further below.
Therefore, an improved clock frequency multiplier that addresses some of the limitations of conventional circuits is desired.